Infinity is an early-stage AI infrastructure research company building the software layer that makes non-NVIDIA chips competitive for AI inference. Rather than relying on scarce human kernel engineers, we use AI to automatically generate, test, and optimize the low-level code that determines how efficiently a chip runs AI models. We've signed or are negotiating design partnerships with d-Matrix, AMD, AWS Trainium, Microsoft (Maia and Nexus), Qualcomm, and others. Founded by Jeremy Nixon (former Google Brain; co-founder of AGI House with Andrej Karpathy), Infinity has raised $15M from investors including the founder of Intercom, the VP of AI at AMD, and the founder of MLCommons. We're headquartered in San Francisco.
The fastest way we've found to make a kernel faster is to let an AI rewrite it and prove, empirically, that the rewrite actually won. Systems like AlphaEvolve made the shape of this loop clear: propose a change, evaluate it against the version it replaces, keep it only when it's measurably better, and repeat that thousands of times. What comes out the other side is code no person sat down and wrote, and it beats the code a person did.
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Every accelerator that comes online needs an inference stack, and today that stack is hand-built per chip, per model, per optimization - a permanent, growing backlog of engineering work that scales linearly with the number of chips and models in the world.
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Bringing a new AI accelerator from bare firmware to running state-of-the-art open-source LLMs takes months to years today. It spans firmware, kernel drivers, toolchains, compilers, kernels, runtime, and the inference stack — almost all of it written by hand, per chip.
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Everything upstream of us is gated by one scarce resource: the chip itself. A part is under NDA, or taped out but not yet back from the fab, or there are four boards on earth and all four are booked. That scarcity sets the pace of the entire company, until you take the hardware off the critical path.
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You can't optimize what you can't measure, and on a fresh accelerator there is usually nothing to measure with - no Nsight, no rocprof, no performance counters anyone has documented how to read. Visibility today is a per-vendor artifact, hand-built by the people who shipped the silicon, so every chip without a mature profiler leaves engineers optimizing in the dark until someone ports one over by hand. And even where a profiler exists, most of them hand you data instead of an answer: a thousand numbers that never say which one is the bottleneck.
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Debugging an accelerator usually means chasing something that is already gone. A run hangs, a race condition fires, or a result refuses to reproduce, and the state that would explain it evaporated the moment execution moved on. The standard recourse is to instrument more, run again, and narrow in one increasingly detailed dump at a time; on non-deterministic failures, that loop may never converge. Numerical bugs are worse to localize by hand, because the corruption usually sits far upstream of where it finally surfaces.
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Every paper published in ML, systems, and hardware research contains dozens to hundreds of concrete, verifiable subtasks: acquire this dataset, implement this kernel, reproduce this baseline, hit this number within this tolerance. Today almost none of that gets checked. A paper is either "replicated" by some grad student months later, or it isn't replicated at all - and the field has no reliable way to measure whether an autonomous agent, given a paper and a terminal, can actually do the work.
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